Full Adder using NAND Gate
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Author: YASHIN

Project access type: Public

Description:

 The full-adder has three inputs and two outputs. The first two inputs are A and B and the third input is an input carry. When a full adder logic is designed we will be able to string eight of them together to create a byte-wide adder and cascade the carry bit from one adder to the next.

Created: Dec 09, 2024

Updated: Dec 09, 2024


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