project.name

Vidura Vihanga

Member since: 4 months

Educational Institution: Not Entered

Country: Not Entered

Half Adder

Half Adder
Public
project.name

main circuit output x

main circuit output x
Public
project.name

Full Adder

Full Adder
Public
project.name

JK FlipFlop

JK FlipFlop
Public
project.name

main circuit output x

main circuit output x
Public
project.name

RIPPLE CARRY ADDER

RIPPLE CARRY ADDER
Public
project.name

RIPPLE CARRY ADDER

RIPPLE CARRY ADDER
Public
project.name

simplified main circuit

simplified main circuit
Public
project.name

16 TO 4 ENCODER

16 TO 4 ENCODER
Public
project.name

DECODER 4 TO 16

DECODER 4 TO 16
Public
project.name

Ripple Carry Adder ramsan

Ripple Carry Adder ramsan
Public
project.name