Clocked D latch

Not A or C

temporary

D memory cell

Half Adder

Four-bit register

Workbook page 2

SR latch

D flip-flop

Reading from memory

ALU

NOR with feedback

One-bit ALU

Basic gates

Latches sandbox

Writing to memory

A and B or C

NOR using NANDS

Circuit Question

SR latch

XOR using NOR

Ripple Carry Adder

Memory sandbox

Gated S-R latch

Not gate

D latch

XOR using other gates

Inverting gates

Exclusive gates

A or B and not C

Combi test

Worksheet page 3

Process control

Combi-boiler Control System

OR using NAND and NOTs

AND using NOR and NOTs

All NOR gates

All NAND gates

Four bit adder

2 bit adder

D latch with timing diagram

De Morgan NOR

D flip-flop with timing diagram

Four possible combinations of AND gate inputs

De Morgan NAND

D type latch

Full adder

Full adder using sub-circuits