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Haroon Masih

Member since: 4 years

Educational Institution: UET University

Country: Pakistan

Figure: 3 = Implementation of the 4-bit shift register with parallel load

Figure: 3 = Implementation of the 4-bit shift register with parallel load
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Lab 14 - BCD Counter

Lab 14 - BCD Counter
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6 BIT Comparator

6 BIT Comparator
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4 BIT Comparator

4 BIT Comparator
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SR - LATCH

SR - LATCH
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SR-LATCH WITH CONTROL

SR-LATCH WITH CONTROL
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S'R' - LATCH

S'R' - LATCH
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D - LATCH

D - LATCH
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LAB 13

LAB 13
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4 bit ripple counter

4 bit ripple counter
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Figure: 01 = Simplest 4-bit Shift Register

Figure: 01 = Simplest 4-bit Shift Register
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Lab 14 -2 , Upto - 5 - Counter

Lab 14 -2 , Upto - 5 - Counter
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