planned features added:

-multitasking support -2 user mode registers, 1 kernel mode register

-floating point support

variable execution length: 

fetch+decode - 1 cycle

register read - 1 cycle

ALU execute - 1 cycle

jump execute - 2 cycles

load execute - 2 cycles

store execute - 1 cycle

write back - 1 cycle

(ideas on how to do: add "pause" wire that stops fetch+decode from putting the Uop it is working on into the ALU's read buffer and auto-progressing the PC until execution is finished)

pipeline edits:

primary and secondary decode merged into one, sends Mops to exec port

Mop execution is now grouped by IO rather than instruction format

immediates use the same port as regular instructions

4-stage pipeline

fetch+decode - register read - execute - write back

pipeline bubbles when operation dependencies have not been resolved