This is a 32 bit computer that runs the risc-v 32I user mode instruction set. 

What is risc-v? risc-v is a modern open source cpu architecture.

The computer is currently running a demo program that counts through the triangular sequence in hex, the number is displayed on number display 1 (top right next to screen)  Set the clock speed to 50ms to make the computer run faster

programing 

official risc-v documentation: https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf

risc-v instruction encoder: https://luplab.gitlab.io/rvcodecjs/

online assembler: https://riscvasm.lucasteske.dev/#

eeprom A stores high half word while eeprom B stores lower half word of each instruction.

ram and i/o

ram accesses must be aligned

i/o mapings:

screen ram 0x0600 to 0x06FF    teletyper: 0x0400

number display 1: 0x401     number display 2: 0x0402

instructions

Lui

addi

slti

sltiu

xori

ori

andi

slli

srli

srai

add

sub

sll

slt

sltu

xor

srl

sra

or

and

lb

lh

lw

lbu

lhu

sb

sh

sw

jal

jalr

beq

bne

blt

bge

bltu

bgeu