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universal gate implimentation(P + R + Q) (Q’ + P’ +R) (P +Q’ + R)
universal gate implimentation(P + R + Q) (Q’ + P’ +R) (P +Q’ + R)home task
home task6 bits odd parity Generator
6 bits odd parity GeneratorEVEN PARITY GENERATOR
EVEN PARITY GENERATOR(E.F.G)+(L.M)+(F+L)
(E.F.G)+(L.M)+(F+L)parity checker
parity checkerlab performance 2
lab performance 2lab task 2
lab task 2lab task 2 NOR gate
lab task 2 NOR gatelab performance 3
lab performance 3ASSIGNMENT 1.1
ASSIGNMENT 1.1ASSIGNMENT 1.2
ASSIGNMENT 1.2LAB TASK 3.1
LAB TASK 3.1LAB TASK 3.2
LAB TASK 3.2LAB PERFORMANCE 4.1
LAB PERFORMANCE 4.1LAB PERFORMANCE 4.2
LAB PERFORMANCE 4.2EVEN PARITY CHECKER
EVEN PARITY CHECKER3 bits odd parity
3 bits odd parityLAB PERFORMANCE 5.1
LAB PERFORMANCE 5.1LAB PERFORMANCE 5.2
LAB PERFORMANCE 5.24 bits binary adder
4 bits binary adder5 bits binary adder
5 bits binary adderlab performance 8
lab performance 8home task
home taskLab 1
Lab 14 BIT EVEN PARITY GENERATOR
4 BIT EVEN PARITY GENERATOR