lab5

lab5

4 bit synchronous down counter using jk flip flop

4-bit Calculator

4-Bit To 7-Segment Decoder

1

4.3

lab 4 2

EXPERIMENT 20

Adder subtractor Circuit detail explanation

4 bit adder/subtractor

JK Flip flop

SR Flip Flop

4 bit asynchronous down counter using jk flip flop

7 Segment Display with ROM Encoding

4-bit subtractor

4-bit JK flip-flop counter

Binary to 7 Segment

4 bit synch up/down counter

4 bit up/down counter

counter

lab 8

Lab9

lab 9

Combinational Double Dabble

Lab9