Simple Processor
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Author: KISHAN PATEL

Project access type: Public

Description:

In this task, you’ll design a simple processor that performs arithmetic and logical operations based on instructions stored in RAM. You’ll use four registers (R0-R3) for storing values, CircuitVerse’s inbuilt ALU for operations, and a control unit to manage the instruction cycle.

Understanding the Fetch-Decode-Execute Cycle

The fetch-decode-execute cycle is the process a processor follows to retrieve and execute instructions one by one. Here’s a breakdown of each step in the cycle:

  1. Fetch:

    • The processor starts by fetching (retrieving) the next instruction from memory (RAM).
    • An address register, often called the Program Counter (PC), keeps track of the address of the next instruction to fetch.
    • After fetching an instruction, the PC is updated to point to the next instruction’s address in RAM.
  2. Decode:

    • The fetched instruction is then sent to the Control Unit, which decodes it to understand the operation to be performed and the data needed.
    • In this assignment, instructions are in a 16-bit format:
      • The first 4 bits are the Opcode, which tells the processor what operation to perform.
      • The next 4 bits specify the Destination Register (where to store the result).
      • The final 8 bits specify two Source Registers (the registers holding the operands).
    • The Opcode tells the ALU which operation to perform. The opcodes for this task are:
      • 2 for ADD (addition)
      • 6 for SUB (subtraction)
      • 0 for AND (bitwise AND)
      • 1 for OR (bitwise OR)
  3. Execute:

    • Based on the decoded instruction, the processor performs the specified operation using the Arithmetic Logic Unit (ALU).
    • For example:
      • If the instruction is ADD R0 R1 R2, the processor will retrieve the values from R1 and R2, add them using the ALU, and store the result in R0.
    • The ALU uses CircuitVerse’s inbuilt function, with the appropriate opcode setting to perform the specified operation.
    • Once the operation is completed, the processor goes back to the fetch step to retrieve the next instruction.

Example of an Instruction Execution

Suppose the RAM stores an instruction ADD R0 R1 R2 encoded in binary:

  • The Opcode (2) specifies the ALU should perform an addition.
  • The Destination Register (R0) will store the result.
  • Source Registers (R1 and R2) provide the operands.

Here’s how it would work step-by-step:

  1. Fetch: The instruction ADD R0 R1 R2 is retrieved from RAM.
  2. Decode: The control unit decodes the instruction:
    • Recognizes Opcode 2 as an ADD operation.
    • Identifies R0 as the destination and R1, R2 as sources.
  3. Execute: The ALU adds the contents of R1 and R2, storing the result in R0.


Components Summary:

  • Registers (R0-R3): Used to hold values for operations and store results.
  • RAM: Holds the program’s instructions.
  • ALU: Executes arithmetic/logic operations with the specified opcode.
  • Control Unit: Manages the fetch-decode-execute cycle.


In this processor design using CircuitVerse’s inbuilt RAM, instructions are stored in a 16-bit format, with each instruction split into three parts: the Opcode (first 4 bits), Destination Register (next 4 bits), and Source Registers(last 8 bits, 4 bits each for two sources). The Program Counter (PC) holds the address of the current instruction, and each cycle begins by using the PC to fetch this instruction from RAM. The fetched instruction is then sent to a splitter, which separates it into the Opcode, Destination Register, and Source Registers. The Control Unit uses the Opcode to determine which operation the ALU will perform (e.g., addition, subtraction, bitwise AND, OR). To handle the registers, multiplexers are used to select the appropriate registers based on the bits for Source Registers and route them to the ALU’s input. The ALU then performs the specified operation, with its output directed to the Destination Register. After execution, the PC is incremented to fetch the next instruction, repeating this fetch-decode-execute cycle.

Created: 2 days ago

Updated: 2 days ago


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