half adder using nand gates

EXP 2 half sub

Demultiplexer using logic gates

1x4 Demultiplexer using NAND gates

Half adder full ader half sub full sub

3X8 DECODER

3 Bit Synchronous Up Counter J-K Flip Flops

3 Bit Synchronous Up Counter J-K Flip Flops

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EXPERIMENT1FOR EC

experiment 7

exp7 2

HALF ADDER USING BASIC GATES

Full Adder using NAND Gate

sumeet 7

Demultiplexer using logic gates

1 bit magnitude comparator using basic gates

flip flop 1

1-BIT COMPARATOR CIRCUIT USING NAND GATE

2-BIT MAGNITUDE COMPARATOR USING NAND GATE

filp flop1

EXPERIMENT 5

2:1 MULTIPLEXER

7 bit ckt

jk flip flop using nand gate

Full Adder using NAND Gate

1 bit magnitude comparator using basic gates

1-BIT COMPARATOR CIRCUIT USING NAND GATE

2-BIT MAGNITUDE COMPARATOR USING NAND GATE

3X8 DECODER

jk flip flop using nand gate

3 Bit Synchronous Up Counter J-K Flip Flops

3 Bit Synchronous Up Counter J-K Flip Flops

PROJECT 2.00