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Amrutha R

Member since: 3 months

Educational Institution: Presidency University, Bangalore

Country: India

BASIC GATES

BASIC GATES
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EXPERIMENT NO.4

EXPERIMENT NO.4
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EXPERIMENT NO.5

EXPERIMENT NO.5
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EXPERIMENT NO.2

EXPERIMENT NO.2
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Ex: 7 Implementation of gates using 2X1 multiplexer

Ex: 7 Implementation of gates using 2X1 multiplexer
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EXPERIMENT NO.6(DESIGN OF MULTIPLEXER AND DE-MULTIPLEXER)

EXPERIMENT NO.6(DESIGN OF MULTIPLEXER AND DE-MULTIPLEXER)
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EXPERIMENT NO.1(VERIFICATION OF LOGIC GATES)

EXPERIMENT NO.1(VERIFICATION OF LOGIC GATES)
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EXPERIMENT NO.4 ( HALF ADDER & SUBTRACTOR)

EXPERIMENT NO.4 ( HALF ADDER & SUBTRACTOR)
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EXPERIMENT NO. 4 (FULL ADDER & FULL SUBTRACTOR)

EXPERIMENT NO. 4 (FULL ADDER & FULL SUBTRACTOR)
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EXPT NO.4

EXPT NO.4
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EXPERIMENT NO.3

EXPERIMENT NO.3
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Impliment J-K Flip Flop

Impliment J-K Flip Flop
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3 BIT UP COUNTER USING J-K FLIP FLOP

3 BIT UP COUNTER USING J-K FLIP FLOP
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Digital circuit Simulator online

Digital circuit Simulator online
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EXPERIMENT NO.6(DESIGN OF MULTIPLEXER AND DE-MULTIPLEXER)

EXPERIMENT NO.6(DESIGN OF MULTIPLEXER AND DE-MULTIPLEXER)
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