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SANIYA BANU2

Member since: 2 months

Educational Institution: Presidency University

Country: India

FULL ADDER USING 4:1 MUX

FULL ADDER USING 4:1 MUX
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EXPERIMENT 2

EXPERIMENT 2
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EXPERIMENT1

EXPERIMENT1
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EXPERIMENT 3

EXPERIMENT 3
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EXPERIMENT 4

EXPERIMENT 4
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EXPERIMENT 2

EXPERIMENT 2
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EXPERIMENT 6

EXPERIMENT 6
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1 AND 2-BIT MAGNITUDE COMPARATOR

1 AND 2-BIT MAGNITUDE COMPARATOR
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ENCODERS

ENCODERS
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3 bit counter

3 bit counter
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3:8 Decoder

3:8 Decoder
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4X1 MULTIPLEXER

4X1 MULTIPLEXER
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2 BIT COMPARATOR USING NAND GATES

2 BIT COMPARATOR USING NAND GATES
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2-Bit comparator using basic gates

2-Bit comparator using basic gates
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1 BIT COMPARATOR USING BASIC GATES

1 BIT COMPARATOR USING BASIC GATES
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J K FLIP FLOP USING NAND GATE

J K FLIP FLOP USING NAND GATE
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1 AND 2-BIT MAGNITUDE COMPARATOR

1 AND 2-BIT MAGNITUDE COMPARATOR
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J K FLIP FLOP USING NAND GATE

J K FLIP FLOP USING NAND GATE
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