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VERIFICATION OF LOGIC GATES EXP1
VERIFICATION OF LOGIC GATES EXP1Experiments 2-verification of boolean laws
Experiments 2-verification of boolean lawsExperiment2-verification of booleans law
Experiment2-verification of booleans lawUntitled
UntitledEXPERIMRNT 2-VERIFICATIONOF BOOLEAN LAWS
EXPERIMRNT 2-VERIFICATIONOF BOOLEAN LAWSEXPERIMENT2- verification of Boolean law
EXPERIMENT2- verification of Boolean lawDESIGN &HALFADDER
DESIGN &HALFADDERFULLN SUBTRACTOR
FULLN SUBTRACTORFULL ADDER
FULL ADDER2 BIT using basic gates
2 BIT using basic gates1 BIT MAGNITUDE COMPARATOR
1 BIT MAGNITUDE COMPARATOR2BIT using NAND gates
2BIT using NAND gates