8 to 3

LAB 2

D Flip-Flop

S-R Flip-Flop

3 bit SISO shift

4x1 Multiplexer zharick

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4x1 multiplexer

Asynchronous Binary Up Counter

2b

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Synchronous Binary Up Counter

3 bit PISO shift

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3 bit PIPO shift

J-K Edge-Triggered Flip-Flop

3 bit SIPO shift

1 full adder

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1 question, 3 to 8

Quiz Master-Slave D-Flipflop circuit using NAND gates

S-R latch with NAND gates.

S-R latch with NOR gates

zharick 1

1 zharick

1 zharick

zharick 2 point electronics

zharick 1 point

Logic 2

logic 5

make up exam

3-bit even parity

3-bit odd parity

4-bit even parity

4-bit odd parity

2 to 4 zharick

Octal to Binary Encoder

4 to 2 encoder

Untitled

4 to 16 zharick

Lecture_7_Binary Subtractor_ zharick

Login 1

3 to 8 zharick

zharick 3 point electronics

zharick 1 point electronics

J-K Master/Slave Flip-Flop

D Flip-Flop

2a

Logic 3

zharick lab 2

8x1 Multiplexer

logic 4

Quiz 3-Bit SIPO circuit using Flip-Flops at Gate Level

bit counter using D Flipflops gate level (Using NAND gates and NOR gates)