project.name

Paula Mayorga

Member since: 4 years

Educational Institution: Not Entered

Country: Not Entered

SISO

SISO
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OR law

OR law
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quiz info mux

quiz info mux
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1 bit substractor

1 bit substractor
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PISO

PISO
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SIPO

SIPO
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Synchronous Binary Up Counter

Synchronous Binary Up Counter
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Master-Slave D-Flipflop

Master-Slave D-Flipflop
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Asynchronous Binary Down Counter

Asynchronous Binary Down Counter
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SIPO

SIPO
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D FLIP FLOP

D FLIP FLOP
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8x1 mux

8x1 mux
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4x1 mux

4x1 mux
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SR FLIP FLOP AND

SR FLIP FLOP AND
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D edge triggered flip flop

D edge triggered flip flop
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PIPO

PIPO
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Asynchronous binary up counter

Asynchronous binary up counter
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Synchronous Binary Down Counter

Synchronous Binary Down Counter
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SR FLIP FLOP NOR

SR FLIP FLOP NOR
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JK master/slave flip flop

JK master/slave flip flop
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1fa

1fa
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full adder

full adder
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full adder

full adder
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2

2
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3

3
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el1

el1
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associative law

associative law
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commutative law

commutative law
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distributive law

distributive law
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NAND

NAND
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SOP

SOP
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POS

POS
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binary gray code

binary gray code
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even and odd parity generator

even and odd parity generator
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even and odd parity checker

even and odd parity checker
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2 to 4 decoder

2 to 4 decoder
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3 to 8 decoder

3 to 8 decoder
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3 to 8 quiz

3 to 8 quiz
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3 bit quiz

3 bit quiz
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octal to binary encoder

octal to binary encoder
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4 to 2 priority

4 to 2 priority
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SR flip flop

SR flip flop
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Paula Mayorga is not a collaborator of any project.

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