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Jahnavi Reddy Kandula

Member since: 4 months

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IMPLEMENTATION AND VERIFICATION OF JK FLIPFLOP UDING NAND GATE

IMPLEMENTATION AND VERIFICATION OF JK FLIPFLOP UDING NAND GATE
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verification of boolean laws

verification of boolean laws
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NOR as an Universal Gate

NOR as an Universal Gate
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Untitled

Untitled
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AKSHU

AKSHU
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FULL SUBTRACTOR USING BASIC GATES

FULL SUBTRACTOR USING BASIC GATES
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experiment 7

experiment 7
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AKSHU

AKSHU
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design of multiplexer and de multiplexer using basic and NAND GATES

design of multiplexer and de multiplexer using basic and NAND GATES
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Full subtractor using NAND gate

Full subtractor using NAND gate
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2-bit magnitude comparator using basic gate

2-bit magnitude comparator using basic gate
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1-BIT MAGNITUDE COMPARATIR using Basic and NAND Gate

1-BIT MAGNITUDE COMPARATIR using Basic and NAND Gate
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experiment no. - 8

experiment no. - 8
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