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HALF SUBTRACTOR
HALF SUBTRACTORFULL SUBTRACTOR
FULL SUBTRACTORNAND IN HALF SUBTRACTOR
NAND IN HALF SUBTRACTORNAND IN FULL SUBTRACTOR
NAND IN FULL SUBTRACTORHALF ADDER
HALF ADDERNAND IN HALF ADDER
NAND IN HALF ADDERLOGIC GATES
LOGIC GATESNAND and NOR Implementation
NAND and NOR Implementation2x1 MULTIPLEXER USING BASIC GATES
2x1 MULTIPLEXER USING BASIC GATES1 BIT COMPARATOR USING NAND GATES
1 BIT COMPARATOR USING NAND GATESEXPERIMENT - 3
EXPERIMENT - 3BOOLEAN LAWS
BOOLEAN LAWSFULL ADDER
FULL ADDERNAND in FULL ADDER
NAND in FULL ADDER1 BIT COMPARATOR
1 BIT COMPARATOR2 BIT COMPARATOR
2 BIT COMPARATOR2 BIT COMPARATOR USING NAND GATES
2 BIT COMPARATOR USING NAND GATES1x2 DE-MULTIPLEXER USING BASIC GATES
1x2 DE-MULTIPLEXER USING BASIC GATES2x1 MULTIPLEXER USING NAND GATES
2x1 MULTIPLEXER USING NAND GATES1x2 DE-MULTIPLEXER USING NAND GATES
1x2 DE-MULTIPLEXER USING NAND GATESexp 7
exp 7JK FLIP FLOP USING NAND GATES
JK FLIP FLOP USING NAND GATESDigital circuit Simulator online
Digital circuit Simulator online