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Aditya Naikar

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2 bit magnitude compararors using basic gates

2 bit magnitude compararors using basic gates
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Untitled
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Experiment 4:design of adder substracter circuit

Experiment 4:design of adder substracter circuit
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Experiment 2:Verification Of Boolean Laws

Experiment 2:Verification Of Boolean Laws
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Experiment 1: derivation of AND,OR,NOT ,NOR,XOR and XNOR using NAND gates

Experiment 1: derivation of AND,OR,NOT ,NOR,XOR and XNOR using NAND gates
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Experiment 3: Design of Combinational CirCuits

Experiment 3: Design of Combinational CirCuits
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Derivation of NOT,OR,AND,EX-OR , EX-NOR using NOR gate

Derivation of NOT,OR,AND,EX-OR , EX-NOR using NOR gate
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implementation of FULL Adder using basic gates

implementation of FULL Adder using basic gates
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2-bit magnitude comparators using Nand gates

2-bit magnitude comparators using Nand gates
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Experiment 4:design of adder substracter circuit

Experiment 4:design of adder substracter circuit
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