2 bit asynchronous up counter
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Author: sreedevi

Project access type: Public

Description:

If we used flip-flops with negative-edge triggering (bubble symbols on the clock inputs), we could simply connect the clock input of each flip-flop to the Q output of the flip-flop before it, so that when the bit before it changes from a 1 to a 0, the “falling edge” of that signal would “clock” the next flip-flop to toggle the next bit:


In circuit verse, the flipflop available are positive triggered. So a not gate has to be given immedaitely after each clock

Created: Jun 24, 2021

Updated: Jun 24, 2021


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