Uday kiran
Member since: 10 months
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Experiment 1
Experiment 1
Public
Full Subtractor ( Experiment 5 )
Full Subtractor ( Experiment 5 )
Public
Half Subtractor (Experiment 5)
Half Subtractor (Experiment 5)
Public
Half Adder ( Experiment 4 )
Half Adder ( Experiment 4 )
Public
Full Adder ( Experiment 4 )
Full Adder ( Experiment 4 )
Public
Untitled
Untitled
Public
Experiment 3
Experiment 3
Public
SOP and POS ( Experiment 2 )
SOP and POS ( Experiment 2 )
Public
JK Flipflop using NOR gate
JK Flipflop using NOR gate
Public
S-R Flipflop using NOR gate
S-R Flipflop using NOR gate
Public
D Flipflop using NOR gate
D Flipflop using NOR gate
Public
10 experiment
10 experiment
Public
T Flipflop using NOR gate
T Flipflop using NOR gate
Public
Encoder
Encoder
Public
J-K Flip-flop using NAND gates
J-K Flip-flop using NAND gates
Public
T Flip-flop using NAND gates
T Flip-flop using NAND gates
Public
D Flip-flop using NAND gates
D Flip-flop using NAND gates
Public
10 experiment
10 experiment
Public
RS flip-flop using NAND gates
RS flip-flop using NAND gates
Public
10 experiment
10 experiment
Public
2 to 4 Line Decoder
2 to 4 Line Decoder
Public
4x1 Multiplexer
4x1 Multiplexer
Public
1:4 Demultiplexer using logic gates
1:4 Demultiplexer using logic gates
Public
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