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S VYSHNAVI

Member since: 1 year

Educational Institution: Not Entered

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Untitled
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BASIC GATES

BASIC GATES
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GATE LAWS

GATE LAWS
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Full adder NAND implementation

Full adder NAND implementation
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Full adder NAND implementation

Full adder NAND implementation
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HALF AND FULL ADDER NAND IMPLEMENTATION

HALF AND FULL ADDER NAND IMPLEMENTATION
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EXP 3

EXP 3
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LEVEL 2 EXP 3

LEVEL 2 EXP 3
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1-bit comparator

1-bit comparator
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2:1 Mux

2:1 Mux
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2- bit exp 5

2- bit exp 5
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HALF SUBTRACTOR

HALF SUBTRACTOR
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FULL SUBTRACTOR

FULL SUBTRACTOR
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