project.name

Mallika Reddy R

Member since: 9 months

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1*2 DeMultiplexer Using Basic And NAND Gate

1*2 DeMultiplexer Using Basic And NAND Gate
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2*1 Multiplexer Using Basic And NAND Gates

2*1 Multiplexer Using Basic And NAND Gates
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LEVEL-1[2] Exp-4

LEVEL-1[2] Exp-4
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DISTRIBUTIVE LAW

DISTRIBUTIVE LAW
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IDEMPOTENT LAW

IDEMPOTENT LAW
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ANNULMENT LAW

ANNULMENT LAW
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IDENTITY LAW

IDENTITY LAW
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COMPLEMENT LAW

COMPLEMENT LAW
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COMMUTATIVE LAW

COMMUTATIVE LAW
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ASSOCIATIVE LAW

ASSOCIATIVE LAW
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Associative law

Associative law
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SCENARIO-2

SCENARIO-2
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SCENARIO-1

SCENARIO-1
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ABSORPTION LAW

ABSORPTION LAW
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1-Bit Magnitude Comparator Using Only NAND Gate

1-Bit Magnitude Comparator Using Only NAND Gate
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Demorgans1

Demorgans1
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DE- MORGAN'S2

DE- MORGAN'S2
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LEVEL-1 Exp-4

LEVEL-1 Exp-4
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LEVEL-1(2) Exp-4

LEVEL-1(2) Exp-4
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LEVEL-1 EXP-4

LEVEL-1 EXP-4
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Full adder using basic gates

Full adder using basic gates
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Full Adder Using NAND Gate

Full Adder Using NAND Gate
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Full Subtractor Using NAND Gate

Full Subtractor Using NAND Gate
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Full Subtractor Using Basic Gates

Full Subtractor Using Basic Gates
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2-BIT MAGNITUDE COMPARATOR USING NAND GATE

2-BIT MAGNITUDE COMPARATOR USING NAND GATE
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BASIC GATES USING NOR

BASIC GATES USING NOR
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COMPLEMENT LAW

COMPLEMENT LAW
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Untitled1-Bit Magnitude Comparator Using Basic Gates

Untitled1-Bit Magnitude Comparator Using Basic Gates
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2-Bit Comparator Using Basic Gate

2-Bit Comparator Using Basic Gate
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UNIVERSAL GATES

UNIVERSAL GATES
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Circuit Diagram of JK FlipFlop

Circuit Diagram of JK FlipFlop
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VERIFICATIONOF LOGIC GATE USING 2:1 MUX

VERIFICATIONOF LOGIC GATE USING 2:1 MUX
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BASIC GATES

BASIC GATES
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SPECIAL GATES

SPECIAL GATES
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HALF ADDER

HALF ADDER
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BASIC GATES USING NAND

BASIC GATES USING NAND
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BASIC GATES USING NOR

BASIC GATES USING NOR
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2-BIT USING BASIC GATES

2-BIT USING BASIC GATES
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DE MORGANS LAW

DE MORGANS LAW
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DISTRIBUTIVE LAW

DISTRIBUTIVE LAW
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FULL SUBTRACTOR

FULL SUBTRACTOR
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IDENTITY LAW

IDENTITY LAW
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1-Bit Magnitude Comparator Using Only NAND Gate

1-Bit Magnitude Comparator Using Only NAND Gate
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LEVEL-1 EXP-4

LEVEL-1 EXP-4
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ASSOCIATIVE LAW

ASSOCIATIVE LAW
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IDEMPOTENT LAW

IDEMPOTENT LAW
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DISTRIBUTIVE LAW

DISTRIBUTIVE LAW
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ANNULMENT LAW

ANNULMENT LAW
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SCENARIO-2

SCENARIO-2
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Untitled1-Bit Magnitude Comparator Using Basic Gates

Untitled1-Bit Magnitude Comparator Using Basic Gates
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COMPLEMENT LAW

COMPLEMENT LAW
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UNIVERSAL GATES

UNIVERSAL GATES
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XOR XNOR USING NAND NOR

XOR XNOR USING NAND NOR
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COMMUTATIVE LAW

COMMUTATIVE LAW
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2 BIT USING NAND

2 BIT USING NAND
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1-BIT COMPARATOR

1-BIT COMPARATOR
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HALF SUBTRACTOR

HALF SUBTRACTOR
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FULL ADDER

FULL ADDER
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2 BIT USING BASIC GATES IMP

2 BIT USING BASIC GATES IMP
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COMPLEMENT LAW

COMPLEMENT LAW
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Associative law

Associative law
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ASSOCIATIVE LAW

ASSOCIATIVE LAW
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SCENARIO-1

SCENARIO-1
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DE- MORGAN'S2

DE- MORGAN'S2
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LEVEL-1 Exp-4

LEVEL-1 Exp-4
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2-BIT MAGNITUDE COMPARATOR USING NAND GATE

2-BIT MAGNITUDE COMPARATOR USING NAND GATE
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ANNULMENT LAW

ANNULMENT LAW
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IDEMPOTENT LAW

IDEMPOTENT LAW
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IDENTITY LAW

IDENTITY LAW
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ABSORPTION LAW

ABSORPTION LAW
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LEVEL-1(2) Exp-4

LEVEL-1(2) Exp-4
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2-Bit Comparator Using Basic Gate

2-Bit Comparator Using Basic Gate
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LEVEL1

LEVEL1
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DISTRIBUTIVE LAW

DISTRIBUTIVE LAW
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ABSORPTION

ABSORPTION
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LEVEL-1[2] Exp-4

LEVEL-1[2] Exp-4
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COMMUTATIVE LAW

COMMUTATIVE LAW
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Demorgans1

Demorgans1
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Full Subtractor Using NAND Gate

Full Subtractor Using NAND Gate
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Full Subtractor Using Basic Gates

Full Subtractor Using Basic Gates
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Mallika Reddy R is not a collaborator of any project.

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