project.name

Divesh singh chauhan

Member since: 10 months

Educational Institution: National institute of technology Hamirpur

Country: India

D flip flop

D flip flop
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SR flip flop

SR flip flop
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DEMORGAN'S LAWS,HALF ADDER IMPLEMENTATION AND BINARY TO GREY CODE

DEMORGAN'S LAWS,HALF ADDER IMPLEMENTATION AND BINARY TO GREY CODE
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full adder using nand

full adder using nand
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full substractor using nand

full substractor using nand
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T Flip Flop

T Flip Flop
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Untitled

Untitled
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half adder

half adder
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half substractor using nor

half substractor using nor
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Untitled

Untitled
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half substractor

half substractor
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full substracter

full substracter
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Untitled

Untitled
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half substractor

half substractor
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FULL adder

FULL adder
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Untitled

Untitled
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full adder

full adder
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Untitled

Untitled
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4-BIT RIPPLE CARRY ADDER

4-BIT RIPPLE CARRY ADDER
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JK flip flop

JK flip flop
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T Flip Flop

T Flip Flop
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4Bit ALU

4Bit ALU
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4 BIT ALU

4 BIT ALU
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HALF SUBTRACTOR NAND AND NOR IMPLEMENTATION

HALF SUBTRACTOR NAND AND NOR IMPLEMENTATION
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4 bit carry lookahead adder

4 bit carry lookahead adder
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three 4 bit wallace tree adder

three 4 bit wallace tree adder
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full substractor using nor

full substractor using nor
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project.name
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4 BIT ALU

4 BIT ALU
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4 BIT ALU

4 BIT ALU
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