intermitentes

Exercise B

Exercise A

EXERCISE E _TEAM 6

Mapas K - 4 input

Mapas K - 3 input

contador examen

MUX de 4 A 1

MUX de 2 a 1

SUMADOR 3 binarios dos bits

Untitled

Two bit Subtractor

Logic Gates with Verilog

Logic Gates with Verilog

Divison de 3 bits

ALL GATES with Verilog

All logic gates

Logic Gates with Verilog

Untitled

MEMORIAS: Sensores y Alarmas

HDL individual

contador de 0 a 7 binario

imagen en la matriz

encender LED con aplauso: MOORE

encender LED con aplauso:Mealy

Aplauso para 3 leds