shreya
Member since: 10 months
Educational Institution: presidency University Bengaluru
Country: India
Half subtractor using basic and NAND gate
Half subtractor using basic and NAND gate
Public
EXP4;full adder implementation using only NAND gate
EXP4;full adder implementation using only NAND gate
Public
EXP4;full adder implementation using basic gates
EXP4;full adder implementation using basic gates
Public
exp 3 level 2
exp 3 level 2
Public
DISTRIBUTIVE LAW
DISTRIBUTIVE LAW
Public
EXPT:5--1
EXPT:5--1
Public
FULL SUBTRACTOR USING BASIC GATES
FULL SUBTRACTOR USING BASIC GATES
Public
FULL SABTRACTOR USING ONLY NAND GATE
FULL SABTRACTOR USING ONLY NAND GATE
Public
2 BIT MULTIPLEXER
2 BIT MULTIPLEXER
Public
4x1 n 2x1 multiplexer
4x1 n 2x1 multiplexer
Public
2X1 multiplexer n 1x2 demultiplexer using basic gates
2X1 multiplexer n 1x2 demultiplexer using basic gates
Public
LOGIC GATES
LOGIC GATES
Public
EXP 4;half adder inplementation using basic gates
EXP 4;half adder inplementation using basic gates
Public
2x1 mux using NAND gate
2x1 mux using NAND gate
Public
2x4 DECODER
2x4 DECODER
Public
4x2 ENCODER
4x2 ENCODER
Public
FULL ADDER USING MULTIPLEXER
FULL ADDER USING MULTIPLEXER
Public
EXP 4;half adder implementation using only NAND gate
EXP 4;half adder implementation using only NAND gate
Public
shreya doesn't have any favourites.
