SIDDIQ - Circuits

SIDDIQ

Member since: 3 months

Educational Institution: Not Entered

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Derivation of AND , OR , NOT , XOR , and NOR using NAND GATE.

Derivation of AND , OR , NOT , XOR , and NOR using NAND GATE.

Public

project.name

Implementation of full adder using nand gate

Implementation of full adder using nand gate

Public

project.name

Untitled

Untitled

Public

project.name

AND GATE

AND GATE

Public

project.name

NAND GATE

NAND GATE

Public

project.name

Untitled

Untitled

Public

project.name

EXP 07

EXP 07

Public

project.name

Implementation of full ladder using basic gates

Implementation of full ladder using basic gates

Public

project.name

EXP.NO:03

EXP.NO:03

Public

project.name

LOGIC GATE

LOGIC GATE

Public

project.name

LOGIC GATE

LOGIC GATE

Public

project.name

EXP 04

EXP 04

Public

project.name

EXP 05

EXP 05

Public

project.name

EXP 06

EXP 06

Public

project.name

Derivation of AND , OR , NOT , XOR , and NOR using NAND GATE.

Derivation of AND , OR , NOT , XOR , and NOR using NAND GATE.

Public

project.name

SIDDIQ is not a collaborator of any project.