project.name

JINITH

Member since: 11 months

Educational Institution: PRESIDENCY UNIVERSITY , BANGALORE

Country: India

NAND GATES

NAND GATES
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NOR GATES

NOR GATES
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FULL ADDER

FULL ADDER
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HALF ADDER

HALF ADDER
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Experiment - 1

Experiment - 1
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Untitled

Untitled
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nand

nand
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EXPT - 3 LEVEL - 1

EXPT - 3 LEVEL - 1
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Untitled

Untitled
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2-bit comparator using NAND

2-bit comparator using NAND
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Untitled

Untitled
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Untitled

Untitled
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2 bit comparator

2 bit comparator
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FULL SUBTRACTOR

FULL SUBTRACTOR
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HALF SUBTRACTOR

HALF SUBTRACTOR
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1 bit comparator

1 bit comparator
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2-bit comparator using NAND

2-bit comparator using NAND
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IMPLEMENTATION OF BASIC GATES USING 2:1 MUX

IMPLEMENTATION OF BASIC GATES USING 2:1 MUX
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Design a 3-bit synchronous MOD-3 counter using JK - f/f

Design a 3-bit synchronous MOD-3 counter using JK - f/f
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JK Flip Flop using NAND Gate

JK Flip Flop using NAND Gate
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JINITH is not a collaborator of any project.

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