Preetha S
Member since: 1 year
Educational Institution: Not Entered
Country: Not Entered
Experiment 1 Level 1
Experiment 1 Level 1
Public
Experiment 6
Experiment 6
Public
Experiment 1 level 2
Experiment 1 level 2
Public
Experiment 2
Experiment 2
Public
Experiment 3
Experiment 3
Public
FULL ADDER USING BASIC LOGIC GATES
FULL ADDER USING BASIC LOGIC GATES
Public
FULL ADDER USING NAND GATE
FULL ADDER USING NAND GATE
Public
HALF ADDER
HALF ADDER
Public
Half subtractor using basic gates
Half subtractor using basic gates
Public
Full Subtractor using NAND gate
Full Subtractor using NAND gate
Public
FULL SUBTRACTOR USING BASIC GATES
FULL SUBTRACTOR USING BASIC GATES
Public
1-BIT COMPARATOR CIRCUIT USING NAND GATE
1-BIT COMPARATOR CIRCUIT USING NAND GATE
Public
2-Bit Comparator using NAND gate
2-Bit Comparator using NAND gate
Public
half subtractor using nand gate
half subtractor using nand gate
Public
IMPLEMENTATION OF ALL GATES USING [ 2:1 MUX ]
IMPLEMENTATION OF ALL GATES USING [ 2:1 MUX ]
Public
Untitled
Untitled
Public
2 bit comparator using basic gates
2 bit comparator using basic gates
Public
1 bit magnitude comparator using basic gates
1 bit magnitude comparator using basic gates
Public
3 bit synchronous counter using JK flip flop
3 bit synchronous counter using JK flip flop
Public
