project.name

Mohammed Parvez Khan

Member since: 10 months

Educational Institution: Presidency University Bengaluru

Country: India

Full Adder Using Only NAND Gates

Full Adder Using Only NAND Gates
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Full Subtractor Using Only NAND Gates

Full Subtractor Using Only NAND Gates
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Logic Gates

Logic Gates
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EXP-6 :)

EXP-6 :)
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HALF SUBTRACTOR

HALF SUBTRACTOR
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Half Adder

Half Adder
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Full Adder using Basic gates

Full Adder using Basic gates
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Full Subtractor Using Basic Gates

Full Subtractor Using Basic Gates
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Implementation of gates using NAND and NOR

Implementation of gates using NAND and NOR
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EXP 2 LAWS

EXP 2 LAWS
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EXP 3

EXP 3
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1 bit mohammad magnitude gate

1 bit mohammad magnitude gate
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2 bit magnitude nand and basic

2 bit magnitude nand and basic
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1 bit mohammad magnitude gate

1 bit mohammad magnitude gate
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Exp-7(ii)

Exp-7(ii)
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Exp-7 (i)

Exp-7 (i)
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