project.name

DEEPAK

Member since: 11 months

Educational Institution: Not Entered

Country: Not Entered

Ex-3(Full Adder)

Ex-3(Full Adder)
Public
project.name

Ex-3(Half adder)

Ex-3(Half adder)
Public
project.name

Untitled

Untitled
Public
project.name

Ex -4(Half subtractor)

Ex -4(Half subtractor)
Public
project.name

IMPLEMENTATION OF ALL GATES USING [ 2:1 MUX ]

IMPLEMENTATION OF ALL GATES USING [ 2:1 MUX ]
Public
project.name

EXP-4(FULL SUBSTRACTOR)

EXP-4(FULL SUBSTRACTOR)
Public
project.name

EXP-4 FULL ADDER

EXP-4 FULL ADDER
Public
project.name

Untitled

Untitled
Public
project.name

Ex-3(Full Subtractor)

Ex-3(Full Subtractor)
Public
project.name

Ex-4(1 bit magnitude comparator)

Ex-4(1 bit magnitude comparator)
Public
project.name

Ex-5[level 2(A>B)]

Ex-5[level 2(A>B)]
Public
project.name

Ex-5[level 2(A=B)]

Ex-5[level 2(A=B)]
Public
project.name

0334

0334
Public
project.name

2:1 & 1:2

2:1 & 1:2
Public
project.name

2:1 mux and 1:2 d mux

2:1 mux and 1:2 d mux
Public
project.name

IMPLEMENTATION OF ALL GATES USING [ 2:1 MUX ]

IMPLEMENTATION OF ALL GATES USING [ 2:1 MUX ]
Public
project.name

FULL ADDER CIRCUIT USING 4:1 MULTIPLEXER

FULL ADDER CIRCUIT USING 4:1 MULTIPLEXER
Public
project.name

EXP-4,HALF ADDER

EXP-4,HALF ADDER
Public
project.name
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