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Dhyey patel

Member since: 1 year

Educational Institution: Navrachana University

Country: India

1. Implementation using NAND gate :

1. Implementation using NAND gate :
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FULL ADDER AND SUBTRACTOR

FULL ADDER AND SUBTRACTOR
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Lab - 4

Lab - 4
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To verify De Morgan Throrem by Nand gate

To verify De Morgan Throrem by Nand gate
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2. Implementation using NOR gate

2. Implementation using NOR gate
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multiplexer

multiplexer
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Binary to Gray An Gray to Binary

Binary to Gray An Gray to Binary
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Demux by Dhyey patel

Demux by Dhyey patel
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FLIP FLOP Final

FLIP FLOP Final
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Binary to BCD

Binary to BCD
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Half adder & half subtractor

Half adder & half subtractor
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2-Bit and 3-Bit Counters

2-Bit and 3-Bit Counters
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Demultiplexer(DEMUX)

Demultiplexer(DEMUX)
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Counters final

Counters final
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Multiplexer using gates Final

Multiplexer using gates Final
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