project.name

Surya Ragish

Member since: 11 months

Educational Institution: Not Entered

Country: Not Entered

NAND AS UNIVERSAL GATE

NAND AS UNIVERSAL GATE
Public
project.name

ALL GATES

ALL GATES
Public
project.name

NOR AS UNIVERSAL GATE

NOR AS UNIVERSAL GATE
Public
project.name

VERIFICATION OF BOOLEAN VALUES

VERIFICATION OF BOOLEAN VALUES
Public
project.name

decoders

decoders
Public
project.name

half adder using basic gates and nand gates

half adder using basic gates and nand gates
Public
project.name

combinational circuits

combinational circuits
Public
project.name

2 bit magnitude comparator using basic gates

2 bit magnitude comparator using basic gates
Public
project.name

Untitled

Untitled
Public
project.name

1 bit magnitude comparator using basic gates

1 bit magnitude comparator using basic gates
Public
project.name

DESIGN OF CIRCUITS USING 2X1 MULTIPLEXER

DESIGN OF CIRCUITS USING 2X1 MULTIPLEXER
Public
project.name

DESIGN OF MULTIPLEXER

DESIGN OF MULTIPLEXER
Public
project.name

1 bit magnitude comparator using NAND gate

1 bit magnitude comparator using NAND gate
Public
project.name

SR LATCH AND D LATCH

SR LATCH AND D LATCH
Public
project.name
No result image
Surya Ragish doesn't have any favourites.
No result image
Surya Ragish is not a collaborator of any project.