project.name

kavya jariwala

Member since: 4 months

Educational Institution: Not Entered

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NAND GATE

NAND GATE
Public
project.name

Ex-or gate

Ex-or gate
Public
project.name

OR-NOR gate

OR-NOR gate
Public
project.name

AND-NOR gate

AND-NOR gate
Public
project.name

NOT-NOR gate

NOT-NOR gate
Public
project.name

NAND-NOR gate

NAND-NOR gate
Public
project.name

EX-NOR gate

EX-NOR gate
Public
project.name

HALF-ADDER LOGIC CUIRCUIT

HALF-ADDER LOGIC CUIRCUIT
Public
project.name

HALF-ADDER LOGICAL CIRCUIT

HALF-ADDER LOGICAL CIRCUIT
Public
project.name

HALF - ADDER

HALF - ADDER
Public
project.name

HALF SUBTRACTOR USING AND,NOT,EX-OR

HALF SUBTRACTOR USING AND,NOT,EX-OR
Public
project.name

GRAY-BINARY 4BIT

GRAY-BINARY 4BIT
Public
project.name

BINARY-GRAY

BINARY-GRAY
Public
project.name

GRAY-BINARY 3BIT

GRAY-BINARY 3BIT
Public
project.name

BINARY-GRAY 3BIT

BINARY-GRAY 3BIT
Public
project.name

BINARY-BCD

BINARY-BCD
Public
project.name

NOr gate

NOr gate
Public
project.name

EX-OR gate

EX-OR gate
Public
project.name

asynchronous

asynchronous
Public
project.name

asynchronous

asynchronous
Public
project.name

S-R Fip flop

S-R Fip flop
Public
project.name

D flip flop

D flip flop
Public
project.name

j-k flip flop

j-k flip flop
Public
project.name

t flip-flop

t flip-flop
Public
project.name
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