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DILIPD P2
DILIPD P2DILIP P3
DILIP P3Untitled
UntitledMUX USING NAND GATE
MUX USING NAND GATEDILIP P4
DILIP P4DEMUXPLEXER(1:2)
DEMUXPLEXER(1:2)DILIP P7
DILIP P7Untitled
Untitled1-BIT USING BASIC GATES
1-BIT USING BASIC GATESMULIPLEXER(2:1)
MULIPLEXER(2:1)1-BIT COMPARATOR1
1-BIT COMPARATOR1Untitled
UntitledDEMUX USING NAND GATE
DEMUX USING NAND GATEDILIP P5
DILIP P5DILIP P6
DILIP P6FULL LADDER USING BASIC GATE
FULL LADDER USING BASIC GATEFULL LADDER USING BASIC GATES
FULL LADDER USING BASIC GATESCIRCUITS-8
CIRCUITS-8CIRCUITS-8
CIRCUITS-8CIRCUITS-8
CIRCUITS-81-BIT USING BASIC GATES
1-BIT USING BASIC GATESDILIP P3
DILIP P3(A>B) 2-BIT USING NAND GATE (A=B)
(A>B) 2-BIT USING NAND GATE (A=B)MUX USING BASIC GATE
MUX USING BASIC GATEFULL ADDER CIRCUIT USING 4:1 MUX
FULL ADDER CIRCUIT USING 4:1 MUX2 BIT MAGNTUDE COMPARATOR USING NAND GATE
2 BIT MAGNTUDE COMPARATOR USING NAND GATE