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ANUSHA S ACHARYA

Member since: 11 months

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gate verification

gate verification
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EXP-2

EXP-2
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DEMULTIPLEXER (1:2)

DEMULTIPLEXER (1:2)
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Untitled

Untitled
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HALF SUB USING BASIC GATE

HALF SUB USING BASIC GATE
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HALF SUB USING NAND GATE

HALF SUB USING NAND GATE
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FULL SUB USIMG NAND GATE

FULL SUB USIMG NAND GATE
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MUX USING NAND GATE

MUX USING NAND GATE
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Untitled

Untitled
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exp=2

exp=2
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2 BIT USING NAND GATE (A=B)

2 BIT USING NAND GATE (A=B)
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gate verification

gate verification
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27/02/2024

27/02/2024
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Exp=4 level 1

Exp=4 level 1
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EXP=4 LEVEL 1 (USING NAND GATE)

EXP=4 LEVEL 1 (USING NAND GATE)
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Untitled

Untitled
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DeMorgens law

DeMorgens law
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absorption law

absorption law
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DeMorgens law

DeMorgens law
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Commutative law

Commutative law
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Untitled

Untitled
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DEMUX USING BASIC GATE

DEMUX USING BASIC GATE
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universal gates

universal gates
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half adder subtraction

half adder subtraction
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FULL ADDER CIRCUIT

FULL ADDER CIRCUIT
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FULL ADDER USING BASIC GATE

FULL ADDER USING BASIC GATE
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full adder using basic gates

full adder using basic gates
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FULL ADDER USING BASIC GATE

FULL ADDER USING BASIC GATE
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FULL SUB USING BASIC GATE

FULL SUB USING BASIC GATE
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1 BIT USING BASIC GATE

1 BIT USING BASIC GATE
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1 BIT USING NAND GATE

1 BIT USING NAND GATE
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Untitled

Untitled
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Untitled

Untitled
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Untitled

Untitled
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MUX USING BASIC GATE

MUX USING BASIC GATE
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DEMUX USING NAND GATE

DEMUX USING NAND GATE
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Untitled

Untitled
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FULL ADDER USING 4:1 MUX

FULL ADDER USING 4:1 MUX
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flipflop

flipflop
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DEMULTIPLEXER (1:2)

DEMULTIPLEXER (1:2)
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Untitled

Untitled
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