SANJAN S D
Member since: 5 months
Educational Institution: PRESIDENCY UNIVERSITY , BANGALORE
Country: India
LAW 1,2,3
LAW 1,2,3
Public
LAW 4,5
LAW 4,5
Public
LAW 8
LAW 8
Public
LAW 9
LAW 9
Public
LAW 6
LAW 6
Public
LAW 7
LAW 7
Public
7 gates 2 inputs
7 gates 2 inputs
Public
exp 1 level 2
exp 1 level 2
Public
exp 3 level 1 :logic gates for minterm and maxterm
exp 3 level 1 :logic gates for minterm and maxterm
Public
HALF ADDER USING NAND GATE
HALF ADDER USING NAND GATE
Public
FULL SUBTRACTOR USING BASIC GATES
FULL SUBTRACTOR USING BASIC GATES
Public
EXP 3 LEVEL 2
EXP 3 LEVEL 2
Public
Untitled
Untitled
Public
HALF ADDER USING BASIC GATES
HALF ADDER USING BASIC GATES
Public
HALF SUBTRACTOR USING BASIC GATES
HALF SUBTRACTOR USING BASIC GATES
Public
HALF SUBTRACTOR USING NAND GATE
HALF SUBTRACTOR USING NAND GATE
Public
FULL ADDER USING BASIC GATES\
FULL ADDER USING BASIC GATES\
Public
FULL ADDER USING ONLY NAND GATE
FULL ADDER USING ONLY NAND GATE
Public
implementation of 2bit magnitude comarator level 2 expression 1&2
implementation of 2bit magnitude comarator level 2 expression 1&2
Public
expression for a>b using basic and nand gate
expression for a>b using basic and nand gate
Public
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