project.name

David Jessup

Member since: 10 months

Educational Institution: California State Polytechnic University, Pomona

Country: United States

PE3to2

PE3to2
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ATM Charge Fee

ATM Charge Fee
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Farmer Scenario

Farmer Scenario
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Majority Voting System

Majority Voting System
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Two-Level AND-OR Implementation

Two-Level AND-OR Implementation
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2x4 Decoder to 4x1 MUX

2x4 Decoder to 4x1 MUX
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Student Schedule

Student Schedule
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5-Bit Adder

5-Bit Adder
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4-bit Counter

4-bit Counter
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Traffic Lights

Traffic Lights
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Counter of 1s

Counter of 1s
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Buzzer FSM

Buzzer FSM
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3x8 Decoder

3x8 Decoder
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4x1 Multiplexer

4x1 Multiplexer
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Prime Number

Prime Number
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4-bit Ripple Carry Adder

4-bit Ripple Carry Adder
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Multi-Control Counter

Multi-Control Counter
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Carry Look Ahead Adder

Carry Look Ahead Adder
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RAM-Based 7-Segment Decoder

RAM-Based 7-Segment Decoder
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SR Latch

SR Latch
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Redesigned 7-Segment Decoder

Redesigned 7-Segment Decoder
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Number of 1's Counter (1-bit Adders)

Number of 1's Counter (1-bit Adders)
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Lab 11 A

Lab 11 A
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Mod 6 counter

Mod 6 counter
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W11.3 HW

W11.3 HW
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Final Exam #1

Final Exam #1
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Final Exam #2

Final Exam #2
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