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LATCH USING NAND
LATCH USING NANDLATCH USING NOR
LATCH USING NORFLIPFLOP USING NAND
FLIPFLOP USING NANDQ.3)assignment-2
Q.3)assignment-2ASSIGNMENT-3 Q.6)
ASSIGNMENT-3 Q.6)Q.2) assignment-2
Q.2) assignment-2ASSIGNMENT-3 Q.1)
ASSIGNMENT-3 Q.1)Q.5)HALF SUBTRACTOR
Q.5)HALF SUBTRACTORASSIGNMENT-4
ASSIGNMENT-4ASSIGNMENT-3
ASSIGNMENT-3CS
CSLOGIC GATES
LOGIC GATESLOGIC GATES
LOGIC GATESASSIGNMENT-5
ASSIGNMENT-5Q.2) LOGIC GATES USING NOR
Q.2) LOGIC GATES USING NORSUBTRACTOR
SUBTRACTORADDERS
ADDERSMUX
MUXUntitled
UntitledIMPLEMENT USING MUX
IMPLEMENT USING MUXQ.3)LOGIC GATES USING NAND
Q.3)LOGIC GATES USING NANDQ.1)LOGIC GATES
Q.1)LOGIC GATESQ.4)HALF ADDER
Q.4)HALF ADDERASSIGNMENT-2
ASSIGNMENT-2ASSIGNMENT-3 Q.2)
ASSIGNMENT-3 Q.2)ASSIGNMENT-3 Q.4)
ASSIGNMENT-3 Q.4)ASSIGNMENT-3 Q.5)
ASSIGNMENT-3 Q.5)ALU DESIGN
ALU DESIGNDEC_ASSIGNMENT
DEC_ASSIGNMENT4-Bit BCD Adder
4-Bit BCD AdderDEC_ASSIGNMENT-1
DEC_ASSIGNMENT-1SEQUENTIAL CIRCUIT
SEQUENTIAL CIRCUITDEC_ASSIGNMENT-2
DEC_ASSIGNMENT-2FLIPFLOP USING NOR
FLIPFLOP USING NORECL Lab 5
ECL Lab 5