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Author: TMSY Tutorials
Project access type: Public
Description:
To write the Verilog code for 4-bit carry adder – cum subtractor and obtain the simulation, synthesis results using Xilinx ISE 14.7 tool.
A full adder is a digital circuit that performs the addition of two binary numbers along with a carry input. It has three inputs: a, b, and cin (carry input), and two outputs: sum and carry.
In this truth table, ‘a’ and ‘b’ are the two input bits, ‘cin’ is the carry input, ‘sum’ is the sum output, and ‘carry’ is the carry output. The full adder circuit can be implemented using logic gates such as AND, OR, and XOR gates. In this truth table, ‘a’ and ‘b’ are the two input bits, ‘cin’ is the carry input, ‘sum’ is the sum output, and ‘carry’ is the carry output. The full adder circuit can be implemented using logic gates such as AND, OR, and XOR gates.
A full adder can be used as a building block for constructing larger adders such as a ripple-carry adder, carry-lookahead adder, or carry-select adder.
A full subtractor is a digital circuit that performs the subtraction of two binary digits and produces a difference and a borrow. Similar to a full adder, a full subtractor takes into account a borrow input from previous stages of subtraction.
A full subtractor has three inputs, ‘a’, ‘b’, and ‘bin’ (borrow in), and two outputs, ‘difference’ and ‘borrow’.
In this truth table, the ‘difference’ output difference is the XOR of the input bits ‘a’ and ‘b’ and the ‘borrow’ output is the AND of the complement of ‘a’ and ‘b’, as well as the complement of the borrow input ‘bin’.
A full subtractor can be implemented using logic gates such as XOR, AND, and NOT gates. A cascade of full subtractors can be used for performing multi-bit subtraction. However, similar to the ripple carry adder, the ripple borrow propagate delay can lead to longer propagation delays for multi-bit subtraction.
Figure 1 Block Diagram of 4-bit Adder and Subtractor
Figure 2 Simulated Diagram of 4-bit Adder and Subtractor when cin = 0
Figure 3 Simulated Diagram of 4-bit Adder and Subtractor when cin = 1
module fulladder(sum,carry,a,b,cin); output sum; output carry; input a; input b; input cin; wire w1,w2,w3; xor x1(w1,a,b); and x2(w2,a,b); xor x3(sum,w1,cin); and x4(w3,w1,cin); or x5(carry,w2,w3); endmodule
Step 2: 4-Bit Carry Adder cum Subtractor
module binary_adder_subtractor(sum,cout,a,b,cin); output [3:0]sum; output cout; input [3:0]a,b; input cin; wire c0,c1,c2; wire w1,w2,w3,w4; xor n1(w1,b[0],cin); xor n2(w2,b[1],cin); xor n3(w3,b[2],cin); xor n4(w4,b[3],cin); fulladder FA0(sum[0],c0,a[0],w1,cin); fulladder FA1(sum[1],c1,a[1],w2,c0); fulladder FA2(sum[2],c2,a[2],w3,c1); fulladder FA3(sum[3],cout,a[3],w4,c2); endmodule
TEST BENCH:
module binary_adder_subtractor_TB; // Inputs reg [3:0] a; reg [3:0] b; reg cin; // Outputs wire [3:0] sum; wire cout; binary_adder_subtractor uut(sum,cout,a,b,cin); initial begin $monitor($time,"a=%b,b=%b,cin=%b,cout=%b,sum=%b",a,b,cin,cout,sum); // Initialize Inputs a = 4'b0000; b = 4'b0000; cin = 1'b0; end always #20 a = a + 1; always #10 b = b + 1; always #05 cin = cin + 1; endmodule
The Synthesis and Simulation results for the 4-bit Carry Adder cum Subtractor are obtained using the Xilinx ISE 14.7 tool.
Created: Apr 01, 2024
Updated: Apr 01, 2024
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