ece 366 hw
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Author: Schutfort Elsa A02392875

Forked from: Ibrahim Sagir/ece 366 hw

Project access type: Public

Description:

Q1 ISA and Circuitverse practice

10 Points

Grading comment:

Implement (on circuitverse.org) a CPU supporting a tiny ISA (see below) including:

  • 4 registers (R0 - R3), each is 32-bit in width
  • 5 instructions {init, addi, sltR0, bezR0, halt}

Here is a python simulator for this subset of instructions: https://replit.com/@raowenjing/myTinyISA-sim#main.py

Main components of your system:  

  • Instruction memory: a ROM module with 16 bytes
  • PC logic (automatically +1, unless modified by bezR0)
  • ALU: supporting {add, slt} operations.
  • Register File: containing R0 - R3 with 2 read ports and 1 write port.
  • Control Unit: able of generating corresponding MUX selection signals based on instruction opcode.

Top-level System IO:

  • System input: 1-bit input serving as clock signal.
  • A reset signal to clear PC = 0.
  • System output: various displays (can include hex LEDs) for the content of PC and each register.

Instruction list :

hw6.jpg

Example program:

hw7.png

Initialize a ROM module with the above example code, such that after 15 cycles we'll see (R0 - R4) = (1, 4, 6, 0)

Created: Apr 02, 2024

Updated: Apr 02, 2024


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