project.name

SHIVANANDA AP"20231CSE3039"

Member since: 5 months

Educational Institution: Not Entered

Country: Not Entered

4:1 MUX

4:1 MUX
Public
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Realization of 1:4 DEMUX Using Basic Gates

Realization of 1:4 DEMUX Using Basic Gates
Public
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basic gate using NAND gate

basic gate using NAND gate
Public
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AND GATE

AND GATE
Public
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OR gate

OR gate
Public
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NOT gate

NOT gate
Public
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EXOR gate

EXOR gate
Public
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NOR gate

NOR gate
Public
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NAND gate

NAND gate
Public
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EX-NOR gate

EX-NOR gate
Public
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basic gate using NOR gate

basic gate using NOR gate
Public
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2bit half subtractor

2bit half subtractor
Public
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4:2 PRIORITY

4:2 PRIORITY
Public
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2:1 MUX Using Universal Gate

2:1 MUX Using Universal Gate
Public
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4:1 MUX Using Universal Gate

4:1 MUX Using Universal Gate
Public
project.name

2:1 DEMUX Using Universal Gate

2:1 DEMUX Using Universal Gate
Public
project.name

4:1 Demux Using Universal Gate

4:1 Demux Using Universal Gate
Public
project.name

4:1 Demux Using Universal Gate

4:1 Demux Using Universal Gate
Public
project.name

4:1 MUX Using Universal Gate

4:1 MUX Using Universal Gate
Public
project.name

Realization of 2:1 Using Basic and XOR Gate

Realization of 2:1 Using Basic and XOR Gate
Public
project.name

Realization of 1:4 DEMUX Using Basic Gates

Realization of 1:4 DEMUX Using Basic Gates
Public
project.name

1:4 DEMUX

1:4 DEMUX
Public
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1:2 Demux

1:2 Demux
Public
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2:1 MUX

2:1 MUX
Public
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Realization of 2:1 Using Basic and XOR Gate

Realization of 2:1 Using Basic and XOR Gate
Public
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1:2 DEMUX Uisng Basic Gate

1:2 DEMUX Uisng Basic Gate
Public
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1:4 DEMUX

1:4 DEMUX
Public
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4:2 ENCODER

4:2 ENCODER
Public
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construct basic gate using nand gate

construct basic gate using nand gate
Public
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2 bit half adder nand

2 bit half adder nand
Public
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half subractor using nand gate only

half subractor using nand gate only
Public
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2 bit half adder

2 bit half adder
Public
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full subtractor using NAND gate only

full subtractor using NAND gate only
Public
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full adder using NAND gate only

full adder using NAND gate only
Public
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Untitled

Untitled
Public
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Untitled

Untitled
Public
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Realization of 4:1 MUX Using Basic Gates and XOR Gate

Realization of 4:1 MUX Using Basic Gates and XOR Gate
Public
project.name

3 bit asynchrouns up counter

3 bit asynchrouns up counter
Public
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1:2 Demux

1:2 Demux
Public
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Realization of 1:4 DEMUX Using Basic Gates

Realization of 1:4 DEMUX Using Basic Gates
Public
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filpflop

filpflop
Public
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Realization of 2:1 Using Basic and XOR Gate

Realization of 2:1 Using Basic and XOR Gate
Public
project.name

2:1 MUX Using Universal Gate

2:1 MUX Using Universal Gate
Public
project.name

4:1 MUX Using Universal Gate

4:1 MUX Using Universal Gate
Public
project.name

2:1 DEMUX Using Universal Gate

2:1 DEMUX Using Universal Gate
Public
project.name

4:1 Demux Using Universal Gate

4:1 Demux Using Universal Gate
Public
project.name

Realization of 1:4 DEMUX Using Basic Gates

Realization of 1:4 DEMUX Using Basic Gates
Public
project.name

4:1 MUX

4:1 MUX
Public
project.name

Realization of 4:1 MUX Using Basic Gates and XOR Gate

Realization of 4:1 MUX Using Basic Gates and XOR Gate
Public
project.name

2:4 DECODER

2:4 DECODER
Public
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3 BIT SYNCHRONOUS UP/DOWN COUNTER

3 BIT SYNCHRONOUS UP/DOWN COUNTER
Public
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Untitled

Untitled
Public
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3 bit asynchrouns down counter

3 bit asynchrouns down counter
Public
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mama viva

mama viva
Public
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