F22605004 Digital Logic Design Lab 07
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Author: Israr Qayyum

Project access type: Public

Description:

Implement 3-bit carry look-ahead adder.

sample input
A2A1A0= 110
B2B1B0= 101
expected output
S2S1S0 = 011, C3= 1

Created: Jan 01, 2024

Updated: Jan 01, 2024


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