project.name

JEEVAN GOUDA "20231CSE3072"

Member since: 7 months

Educational Institution: Not Entered

Country: Not Entered

FULL ADDER AND FULL SUBSTRACTOR

FULL ADDER AND FULL SUBSTRACTOR
Public
project.name

4:2 PRIORITY ENCODER

4:2 PRIORITY ENCODER
Public
project.name

4:2 ENCODER

4:2 ENCODER
Public
project.name

EXP-3

EXP-3
Public
project.name

4:1 MUX

4:1 MUX
Public
project.name

HALF

HALF
Public
project.name

paralel adder

paralel adder
Public
project.name

full

full
Public
project.name

half sub

half sub
Public
project.name

3 BIT SYNCHRONOUS UP AND DOWN

3 BIT SYNCHRONOUS UP AND DOWN
Public
project.name

4 BIT SYNCHRONOUS UP COUNTER

4 BIT SYNCHRONOUS UP COUNTER
Public
project.name

HALF AND FULL

HALF AND FULL
Public
project.name

Untitled

Untitled
Public
project.name

Nandgate

Nandgate
Public
project.name

HALF ADDER AND HALF SUBTRACTOR

HALF ADDER AND HALF SUBTRACTOR
Public
project.name

DESIGN OF LOGIC DAIGRAM USING BASIC GATE

DESIGN OF LOGIC DAIGRAM USING BASIC GATE
Public
project.name

DESIGN LOGIC GATE USING LOGIC GATE

DESIGN LOGIC GATE USING LOGIC GATE
Public
project.name

FLIP-FLOP

FLIP-FLOP
Public
project.name

MUX AND DEMUX

MUX AND DEMUX
Public
project.name

LOGIC CIRCUIT OF 2 TO 1 MULTIFLEXER

LOGIC CIRCUIT OF 2 TO 1 MULTIFLEXER
Public
project.name

2-TO-4 DECODER

2-TO-4 DECODER
Public
project.name

Untitled

Untitled
Public
project.name

3 BIT ASYNCHRONOUS BINARY DOWN COUNTER

3 BIT ASYNCHRONOUS BINARY DOWN COUNTER
Public
project.name

3 BIT ASYNCHRONOUS BINARY DOWN COUNTER

3 BIT ASYNCHRONOUS BINARY DOWN COUNTER
Public
project.name

JK FLIP FLOP IMPLEMENTING USING NAND GATE

JK FLIP FLOP IMPLEMENTING USING NAND GATE
Public
project.name
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