Member since: 12 months
Educational Institution: Presidency University, Bangalore
Country: India
Half Adder
Half Adder4:2 Priority Encoder
4:2 Priority EncoderFull Subtractor
Full SubtractorNOR Implementation
NOR Implementation8:3 Encoder
8:3 Encoder4:2 Encoder
4:2 Encoder2:1 MUX
2:1 MUXFlipFlops
FlipFlopsHalf Subtractor
Half Subtractor1-Bit Comparator
1-Bit Comparator8:1 MUX
8:1 MUX1:2 DeMUX
1:2 DeMUXNAND Implementation
NAND Implementation2-Bit Comparator
2-Bit Comparator1:4 DeMUX
1:4 DeMUXFull Adder
Full Adder4:1 MUX
4:1 MUXAsynchronous Down Counter Using T-flip flop
Asynchronous Down Counter Using T-flip flopAll gates implementation
All gates implementation