project.name

T.sai sreekar

Member since: 1 year

Educational Institution: Not Entered

Country: Not Entered

Untitled

Untitled
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half adder and half subtractor

half adder and half subtractor
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basic gates

basic gates
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1 bit magnitude

1 bit magnitude
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full adder by using

full adder by using
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Untitled

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Untitled

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Expt-7 l2

Expt-7 l2
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EXPERIMENT 2

EXPERIMENT 2
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JK

JK
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expt 6 Flip flops

expt 6 Flip flops
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JK

JK
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JK to D

JK to D
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EXpt4

EXpt4
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EXpt 2 l2

EXpt 2 l2
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4 bit counter

4 bit counter
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Expt5 l-1

Expt5 l-1
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jk to d

jk to d
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EXPERIMENT 2

EXPERIMENT 2
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Expt5 l-1

Expt5 l-1
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1:2 and 1:4 demux

1:2 and 1:4 demux
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EXPT-3 ALL LEVEL

EXPT-3 ALL LEVEL
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