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Author: Ruben Hillier
Project access type: Public
Description:
It's not working. I have instead made a 1-bit CPU, which you can find on my profile.
CPU architecture for a simple calculator:
Instruction set:
1. NOP(0000) – no operation.
2. AND(0001) – checks if the accumulator is the same as data in memory at the current address, then sets the accumulator to 1 if it is.
3. OR(0010) – if either the accumulator or data in memory at the current address are not 0, then set the accumulator to 1.
4. ADD(0011) – adds data from memory at the current address to the accumulator.
5. SUB(0100) – subtracts the accumulator by data in memory at the current address.
6. LDA(0101) – loads data from memory at the current address into the accumulator.
7. STA(0111) – transfers the data in the accumulator to the next memory address, setting the accumulator to 0.
8. IN1(1000) – load data from the first input register into the accumulator.
9. IN2(1001) – load data from the second input register into the accumulator.
10. OUT1(1010) – transfers the current data in the accumulator to the first output register but does is not reset the accumulator.
11. OUT2(1011) – transfers the current data in the accumulator to the second output register but does is not reset the accumulator.
12. JMP(1100) – adds the data at the current memory address to the program counter.
13. JZADD(1101) – will ADD the memory at the current address to the program counter if the accumulator is 0.
14. JZSUB(1110) – will subtract the memory at the current address to the program counter if the accumulator is 0.
15. HLT(1111) – Halt the execution of data.
Flags:
1. C – The carry flag will be a 1-bit register that is part of the accumulator that will let the ALU know if it needs to consider a carry in a future cycle or when outputting to the output register; this flag will be put as the first digit of the output-2 registers if the number is within 4 bits but with a carry.
2. B – The borrow flag will be a 1-bit register next to the accumulator
The architecture of CPU:
· 8-bit memory address
· 4-bit data bus
· 4-bit instruction set
· Times two 4-bit register inputs.
· Times two 4-bit register outputs.
Created: Nov 28, 2023
Updated: Oct 04, 2024
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