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John W McMichen

Member since: 6 months

Educational Institution: Cleveland State Community College

Country: United States

NAND RS flip-flop

NAND RS flip-flop
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NOR Gate

NOR Gate
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NAND edge-triggered RS flip flop

NAND edge-triggered RS flip flop
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NAND Gate with Clock and LED

NAND Gate with Clock and LED
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NOR Gate Equivalent

NOR Gate Equivalent
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AND Gate

AND Gate
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OR Gate

OR Gate
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NAND Gate

NAND Gate
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DeMorgan's Theorem 1

DeMorgan's Theorem 1
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7 segment display hex

7 segment display hex
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Figure 4-21

Figure 4-21
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Negative Edge Triggered Clock

Negative Edge Triggered Clock
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Full Adder Circuit

Full Adder Circuit
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Half Adder Circuit

Half Adder Circuit
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Positive Edge-triggered clock

Positive Edge-triggered clock
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Full Subtractor Circuit

Full Subtractor Circuit
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D Flip-Flop with positive edge triggered clock

D Flip-Flop with positive edge triggered clock
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4 AND

4 AND
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4 input AND

4 input AND
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JK FF c PRE & CLR

JK FF c PRE & CLR
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JK FF c PRE & CLR

JK FF c PRE & CLR
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ROM access circuit

ROM access circuit
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NAND JK FF backup

NAND JK FF backup
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Ripple Up Counter

Ripple Up Counter
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Hex 7 segment display

Hex 7 segment display
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Roulette Wheel or Marquee Sign

Roulette Wheel or Marquee Sign
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Repeat add multiplier (1)

Repeat add multiplier (1)
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JK FF active low preset and clear

JK FF active low preset and clear
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JK FF with subcircuit

JK FF with subcircuit
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Defective JK flip flop with manual clock

Defective JK flip flop with manual clock
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Recirculating Shift Register D flip flops

Recirculating Shift Register D flip flops
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Decade Ripple Counter

Decade Ripple Counter
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D Flip-Flop with clock

D Flip-Flop with clock
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D Flip-Flop

D Flip-Flop
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Repeated Addition Multiplier

Repeated Addition Multiplier
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AND/OR circuit with clock

AND/OR circuit with clock
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2's Complement Adder/Subtractor

2's Complement Adder/Subtractor
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4 Bit SRAM Memory

4 Bit SRAM Memory
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16 Bit Column Row Decoder

16 Bit Column Row Decoder
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Synchronous Up Counter

Synchronous Up Counter
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Synchronous Down Counter

Synchronous Down Counter
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Serial Load Shift Register, D flip flops

Serial Load Shift Register, D flip flops
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RAM Circuit

RAM Circuit
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8 bit binary to decimal converter

8 bit binary to decimal converter
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Binary Coded Decimal Circuit for 3 digits

Binary Coded Decimal Circuit for 3 digits
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J-K Positive Edge Trigger Flip Flop

J-K Positive Edge Trigger Flip Flop
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JK Master Slave Flip Flop

JK Master Slave Flip Flop
Public
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JK Master-Slave PRE and CLR

JK Master-Slave PRE and CLR
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Password Keyboard Project

Password Keyboard Project
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Half Subtractor

Half Subtractor
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BCD Adder

BCD Adder
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Junk circuit

Junk circuit
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8 Bit Counter

8 Bit Counter
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4 Bit Subtractor: "A - B"

4 Bit Subtractor: "A - B"
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4 Bit Adder: "A + B"

4 Bit Adder: "A + B"
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J-K Flip Flop with inverted clock

J-K Flip Flop with inverted clock
Public
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Defective JK Flip Flop

Defective JK Flip Flop
Public
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Ripple Down Counter

Ripple Down Counter
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XOR Gate

XOR Gate
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AND Gate with Clock and LED

AND Gate with Clock and LED
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XOR Gate with Clock and LED

XOR Gate with Clock and LED
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XNOR Gate

XNOR Gate
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Inverter Gate with Clock and LED

Inverter Gate with Clock and LED
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NOT Gate (Inverter)

NOT Gate (Inverter)
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NAND RS flip-flop with clock

NAND RS flip-flop with clock
Public
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NOR Gate with Clock and LED

NOR Gate with Clock and LED
Public
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DeMorgan's Theorem 2

DeMorgan's Theorem 2
Public
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OR Gate with CLock and LED

OR Gate with CLock and LED
Public
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Serial Waveform Shift Register D flip flops

Serial Waveform Shift Register D flip flops
Public
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Parallel Input, Parallel Output Register, D flip flops

Parallel Input, Parallel Output Register, D flip flops
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Shift and Add Multiplier

Shift and Add Multiplier
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Binary to Hex to Decimal Converter

Binary to Hex to Decimal Converter
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