0-7數字跑馬燈

NOT NOT NOT (Involution)

em-1-013- minterm maxterm

SOP-2 variables

bcd ripplecounter

2-All NAND Implementation F=A(CD+B)+BC

1.9 Binary Logic-01

1.9 Binary Logic-03

1.9 Binary Logic-02

1.9 Binary Logic-04

1.9 Binary Logic-06

1.9 Binary Logic-01-1

1.9 Binary Logic-07

1.9 Binary Logic-07-2

All NAND Implementation F=A(CD+B)+BC'

AND Gate test

Date Matching 1

Date Matching 2

Date Matching 2 w Equivalent

NAND for Inverter

NAND for AND

NAND for OR

Random 座號

呼高富帥=呼

How to simplify a circuit?

Two Level NAND- example 3.9

F1=F4=F5

Timing Diagram Demo

SOP- 3 Variables

SOP VS POS vs Original

XOR with NAND

4-bit Odd parity bit generator

8 bit parity checker

Even Parity XOR: 3 bits generator and 4 bits checker

XOR transmission Even Parity Checker

em-01-010 F=(A+C)(B+C')

em-1-013 (simplification)

A'B'C+A'BC'+A'BC+AB'C+A'B'C'=A'+AB'C

K-map 3 variables. x'yz+xy'+yz'

高 或 (高且富)- Absorption Theorem

full adder SOP half adder encoder

LAB 1

4-Bit Binary Adder

HEX

Splitter

BCD ADDER

Untitled

5 bit adder

Latch with NOR

4-Bit Binary Adder

4x3 array multiplier

4x3 multiplier

8 to 3 line encoder Y input A output

4x2 Priority Encoder

4 : 1 multiplexer

MUX Built using Decoder

4 Bit magnitude comparator

4-Bit Binary Adder with Parity Checking

D-Latch D- Flip Flop

5 bit adder

Full Adder from 2 Half Adders

Serial In Serial Out Shift Register - D flip flop

BCD ripple counter

Ring Counter

4-Bit Swith Tail Ring Counter

8 Bit CPU

Test

4-Bit synchronous Binary counter

4-bit binary synchronous counter using JK flip flop

COUNTERS

Decoder 3 to 8 line with Random Input and LED

ROM

Static RAM