project.name

Vineet Kumar Pandey

Member since: 1 year

Educational Institution: ajay kumar garg engineering collage ghaziabad

Country: India

Untitled

Untitled
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multiplexer

multiplexer
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binary to grey

binary to grey
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half adder

half adder
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cddd

cddd
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8 bit input output system with four 8-bit internal registers

8 bit input output system with four 8-bit internal registers
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1 bit Register

1 bit Register
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8 bit input output system with four 8-bit internal registers

8 bit input output system with four 8-bit internal registers
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ALU8bit

ALU8bit
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ALU8bit

ALU8bit
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ALU8bit

ALU8bit
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8-Bit Carry Look Ahead Adder

8-Bit Carry Look Ahead Adder
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8BIT REGISTER

8BIT REGISTER
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data path pr7

data path pr7
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8 bit ALU from 1 bit ALU

8 bit ALU from 1 bit ALU
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ALU8bit

ALU8bit
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4-bit-carry-lookahead-adder

4-bit-carry-lookahead-adder
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8-Bit Memory Register

8-Bit Memory Register
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8:1 Mux using Logic Gates

8:1 Mux using Logic Gates
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8:1 Mux using Logic Gates

8:1 Mux using Logic Gates
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8 BIT ALU

8 BIT ALU
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3X8 DECODER

3X8 DECODER
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ALU8bit

ALU8bit
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3 to 8 line decoder

3 to 8 line decoder
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ALU8bit

ALU8bit
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8:1 Mux using Logic Gates

8:1 Mux using Logic Gates
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