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Thomas Street

Member since: 577 days

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4 Bit Adder

4 Bit Adder
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4 Bit Adder

Exercse 1

Exercse 1
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Exercse 1

SR Flip Flops

SR Flip Flops
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SR Flip Flops

7 Segment

7 Segment
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7 Segment

4 Input Mux

4 Input Mux
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4 Input Mux

Distributive Law:

Distributive Law:
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Distributive Law:

Distributive Law

Distributive Law
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Distributive Law

Assumption Law

Assumption Law
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Assumption Law

Absorption Law

Absorption Law
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Absorption Law

Absorption Law

Absorption Law
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Absorption Law

Absorption Law 2

Absorption Law 2
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Absorption Law 2

Mux

Mux
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Mux

Priority

Priority
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Priority

ALU

ALU
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ALU

Demux

Demux
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Demux

Exercse 1

Exercse 1
Public
Exercse 1

Simulation 11

Simulation 11
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Simulation 11

Simulation 11

Simulation 11
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Simulation 11

Simulation 1

Simulation 1
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Simulation 1

Simulation 3

Simulation 3
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Simulation 3

Simulation 4

Simulation 4
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Simulation 4

Simulation 4

Simulation 4
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Simulation 4

Simulation 5

Simulation 5
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Simulation 5

Simulation 6

Simulation 6
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Simulation 6

Gated SR

Gated SR
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Gated SR

JK

JK
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JK

3 Bit Sync Counter

3 Bit Sync Counter
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3 Bit Sync Counter

Exercise 01 - Introduction to Digital Gates

Exercise 01 - Introduction to Digital Gates
Public
Exercise 01 - Introduction to Digital Gates

Demorgans

Demorgans
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Demorgans

Decoder

Decoder
Public
Decoder

Simulation 2

Simulation 2
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Simulation 2

Untitled

Untitled
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Untitled

Test 1

Test 1
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Test 1
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